IBS, Daejeon, Republic of Korea
The Rare Isotope Science Project at the Institute for Basic Science constructs the rare isotope accelerator (RAON) facility in South Korea. The stable ion beam as an ion source for the RAON accelerator could be generated by ECR ion source system. Therefore, it is mandatory to build ECR ion source control system that could be integrated into an accelerator control system easily. The vacuum control system is an essential part of the ECR control system, because of one vacuum chamber among three different voltage stages (ground, 50 kV, and 80 kV). The preliminary design and implementation of vacuum control system for the ECR ion source will be discussed. It is planned to use a PLC in order to communicate with a vacuum gauge and turbo pump controllers among multi-voltage stages (ground, 50 kV and 80 kV) by optical fibers connection. The PLC system has two major components: a digital I/O module that provides power to each component and standard RS-232 modules which are connected with the gauge & pump controllers. In addition, its extension plan to integrate the vacuum control system into the RAON accelerator control system based on system the EPICS framework, will be discussed.
IBS, Daejeon, Republic of Korea
RAON is a particle accelerator to research the interaction between the nucleus forming a rare isotope as Korean heavy-ion accelerator. RAON accelerator consists of a number of facilities and equipments as a large-scaled experimental device operating under the distributed environment. For synchronization control between these experimental devices, timing system of the RAON uses the VME-based EVG/EVR system. In order to test the high-speed performance of the control logic with the minimized event signal delay, it is planned to establish the step motor controller testbed applying the FPGA chip. The testbed controller will be configured with Zynq 7000 series of Xilinx FPGA chip. Zynq as SoC (System on Chip) is divided into PS (Processing System) with PL (Programmable Logic). PS with the dual-core ARM cpu is performing the high-level control logic at run-time on linux operating system. PL with the low-level FPGA I/O signal interfaces with the step motor controller with the event signal received from timing system. This paper describes the content and performance evaluation obtained from the step motor control through the various synchronized event signal received from the timing system.