ICALEPCS2015 - List of Authors (Kadyrov, R.A.)

Paper	Title	Page
WEPGF080	Encoder Interface for NSLS-II Beam Line Motion Scanning Applications	881
	R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski BNL, Upton, Long Island, New York, USA
	The variety of motion control applications on existing and future NSLS-II beam lines demand custom control electronics developed to meet specific needs and ease integration to existing systems. Thus an encoder interface was designed for a number of detection techniques that require fly-scan applications. This design fits in a 2U chassis and can handle up to 4 incremental quadrature encoders with a digital RS-422A interface and output frequencies up to 10 MHz. The logic, based on Xilinx Virtex-6 FPGA, processes signals from an encoder, associates it with accelerator timestamp and sends the data to a server using TCP/IP stack, with the server side running an EPICS IOC. Several filtering and compression techniques are also applied. The device then re-translates the interface signals for the motion controller, allowing the device to be installed between encoder and motion controller with no interference to the system. The hardware leverages the NSLS-II BPM Digital Front End (DFE) board with Virtex-6 FPGA and periphery. The design harmoniously complements the family of NSLS-II equipment sharing same mechanical and electrical platform.
	Poster WEPGF080 [4.674 MB]
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Paper

Title

Page

Encoder Interface for NSLS-II Beam Line Motion Scanning Applications

881

R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski
BNL, Upton, Long Island, New York, USA

The variety of motion control applications on existing and future NSLS-II beam lines demand custom control electronics developed to meet specific needs and ease integration to existing systems. Thus an encoder interface was designed for a number of detection techniques that require fly-scan applications. This design fits in a 2U chassis and can handle up to 4 incremental quadrature encoders with a digital RS-422A interface and output frequencies up to 10 MHz. The logic, based on Xilinx Virtex-6 FPGA, processes signals from an encoder, associates it with accelerator timestamp and sends the data to a server using TCP/IP stack, with the server side running an EPICS IOC. Several filtering and compression techniques are also applied. The device then re-translates the interface signals for the motion controller, allowing the device to be installed between encoder and motion controller with no interference to the system. The hardware leverages the NSLS-II BPM Digital Front End (DFE) board with Virtex-6 FPGA and periphery. The design harmoniously complements the family of NSLS-II equipment sharing same mechanical and electrical platform.

Poster WEPGF080 [4.674 MB]

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)