Author: Ha, K.
Paper Title Page
MOC3O05 NSLS-II Fast Orbit Feedback System 34
 
  • Y. Tian, W.X. Cheng, L.R. Dalesio, J.H. De Long, K. Ha, L. Yu
    BNL, Upton, Long Island, New York, USA
  • W.S. Levine
    UMD, College Park, Maryland, USA
  
  This paper pre­sents the NSLS-II fast orbit feed­back (FOFB) sys­tem, in­clud­ing the ar­chi­tec­ture, the al­go­rithm and the com­mis­sion­ing re­sults. A two-tier com­mu­ni­ca­tion ar­chi­tec­ture is used to dis­trib­ute the 10kHz beam po­si­tion data (BPM) around the stor­age ring. The FOFB cal­cu­la­tion is car­ried out in field pro­gram­ma­ble gate ar­rays (FPGA). An in­di­vid­ual eigen­mode com­pen­sa­tion al­go­rithm is ap­plied to allow dif­fer­ent eigen­modes to have dif­fer­ent com­pen­sa­tion pa­ra­me­ters. The sys­tem is used as a reg­u­lar tool to main­tain the beam sta­bil­ity at NSLS-II.  
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TUC3O05 NSLS-II Active Interlock System for Fast Machine Protection 554
 
  • K. Ha, W.X. Cheng, L.R. Dalesio, J.H. De Long, Y. Hu, P. Ilinski, J. Mead, D. Padrazo, S. Seletskiy, O. Singh, R.M. Smith, Y. Tian
    BNL, Upton, Long Island, New York, USA
  • G. Shen
    FRIB, East Lansing, Michigan, USA
  
  Funding: Work supported by DOE contract No: DE-AC02-98CD10886
At Na­tional Syn­chro­tron Light Source-II (NSLS-II), a field-pro­gram­ma­ble gate array (FPGA) based global ac­tive in­ter­lock sys­tem (AIS) has been com­mis­sioned and used for beam op­er­a­tions. The main pro­pose of AIS is to pro­tect in­ser­tion de­vices (ID) and vac­uum cham­bers from the ther­mal dam­age of high den­sity syn­chro­tron ra­di­a­tion power. This re­port de­scribes the sta­tus of AIS hard­ware, soft­ware ar­chi­tec­tures and op­er­a­tion ex­pe­ri­ence. 		 
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WEPGF080 Encoder Interface for NSLS-II Beam Line Motion Scanning Applications 881
 
  • R.A. Kadyrov, J.H. De Long, K. Ha, S. So, E. Stavitski
    BNL, Upton, Long Island, New York, USA
  
  The va­ri­ety of mo­tion con­trol ap­pli­ca­tions on ex­ist­ing and fu­ture NSLS-II beam lines de­mand cus­tom con­trol elec­tron­ics de­vel­oped to meet spe­cific needs and ease in­te­gra­tion to ex­ist­ing sys­tems. Thus an en­coder in­ter­face was de­signed for a num­ber of de­tec­tion tech­niques that re­quire fly-scan ap­pli­ca­tions. This de­sign fits in a 2U chas­sis and can han­dle up to 4 in­cre­men­tal quad­ra­ture en­coders with a dig­i­tal RS-422A in­ter­face and out­put fre­quen­cies up to 10 MHz. The logic, based on Xil­inx Vir­tex-6 FPGA, processes sig­nals from an en­coder, as­so­ci­ates it with ac­cel­er­a­tor time­stamp and sends the data to a server using TCP/IP stack, with the server side run­ning an EPICS IOC. Sev­eral fil­ter­ing and com­pres­sion tech­niques are also ap­plied. The de­vice then re-trans­lates the in­ter­face sig­nals for the mo­tion con­troller, al­low­ing the de­vice to be in­stalled be­tween en­coder and mo­tion con­troller with no in­ter­fer­ence to the sys­tem. The hard­ware lever­ages the NSLS-II BPM Dig­i­tal Front End (DFE) board with Vir­tex-6 FPGA and pe­riph­ery. The de­sign har­mo­niously com­ple­ments the fam­ily of NSLS-II equip­ment shar­ing same me­chan­i­cal and elec­tri­cal plat­form.  
poster icon Poster WEPGF080 [4.674 MB]  
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