TY - CPAPER
AU - Dusatko, J.E.
AU - Cesaratto, J.M.
AU - De Santis, S.
AU - Fox, J.D.
AU - Höfle, W.
AU - Rivetta, C.H.
TI - Upgrade Development Progress for the CERN SPS High Bandwidth Transverse Feedback Demonstrator System
J2 - Proc. of IBIC2014
AB - A high bandwidth feedback demonstrator system has been developed for proof of concept transverse intra-bunch closed loop feedback control studies at the CERN SPS. This system contains a beam pickup, analog front end receiver, signal processor, back end driver, power amplifiers and kicker structure. The main signal processing functions are performed digitally, using very fast (4GSa/s) data converters to bring the system signals into and out of the digital domain. The digital signal processing function is flexibly implemented in an FPGA allowing for maximum speed and reconfigurability for testing multiple control algorithms. The signal processor is a modular design consisting of commercial and custom components. This approach allowed for a rapidly-developed prototype to be delivered in a short time with limited resources. Initial beam studies at the SPS using the system prior to the CERN long shutdown one (LS1) have been very encouraging. We are planning several key upgrades to the system, including the signal processor. This paper describes these upgrades and reports on their progress.
PB - JACoW
CY - Geneva, Switzerland
SP - 700
EP - 702
KW - kicker
KW - feedback
KW - controls
KW - pick-up
KW - timing
DA - 2014/10
PY - 2014
SN - 978-3-95450-141-0
UR - http://jacow.org/IBIC2014/papers/wepd25.pdf
ER -