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TRIUMF is building VECC, the first stage of a 50 MeV electron linac. Beam diagnostic devices will be inserted radially into 8-port vacuum boxes. RF shields, 6.3 cm dia. tubes perforated by pump out slots, can be inserted to reduce wakefields. They will also serve as capacitive probes picking up harmonics of the 650 MHz bunch rate. 100 mV P/P was measured for 3 mA at 100 kV. A SC cavity will accelerate the beam to 10 MeV. The dump current is limited by the shielding to 300 W. We will use a 3 mA beam at 1% duty cycle. Two RF shields will monitor the current. A newly developed circuit will give dc outputs proportional to the peak and average current. It uses a log detector with range of 70 dB for 1 dB of error and a rise and fall time of ~20 ns. Terasic development boards process the log signal. It is digitized by a 14-bit ADC at a 50 MHz rate and passed to a FPGA programmed in Verilog. Altera Megafunctions offset, scale, convert to floating point, antilog and filter the signal in a pipeline architecture. Two 14-bit DACs provide the outputs. Digital processing maintains the wide dynamic range. Beam pulses can be <250 ns and the sample rate insures accuracy at low duty cycle.
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