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- D. Belver, I. Arredondo, P. Echevarria, J. Feuchtwanger, H. Hassanzadegan, M. del Campo
ESS-Bilbao, Zamudio, Spain
- F.J. Bermejo
Bilbao, Faculty of Science and Technology, Bilbao, Spain
- V. Etxebarria, J. Jugo, J. Portilla
University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain
- N. Garmendia, L. Muguira
ESS Bilbao, Bilbao, Spain
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The BPM system from ESS-Bilbao is presented, including test bench, electronics and test results. Our test bench implements 4 capacitive buttons welded to the beam pipe. The position of the internal tube simulating the beam can be changed with respect to the outer tube within a range of 20 mm, with a resolution less than 10 μm. It is connected to an Analog Front-End (AFE) where signals are conditioned and converted to baseband and a Digital Unit (DU) to sample them and calculate the position and phase. The AFE is based on logarithmic amplifiers and IQ demodulators. Signals are converted from differential to single-ended and conditioned to meet the DU requirements (FPGA and ADC). DU includes offset compensation, gain adjustment, CORDIC, delta over σ algorithm and linearization blocks. To manage the FPGA a Java interface has been developed including also the EPICS integration by means of JavaIOC and a MySQL interface. The resolution and accuracy results are promising (less than 10 μm and 1° for the position and phase) provided that the effect of several errors such as temperature variations and nonlinearities are minimized through temperature regulation and system calibration.
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