• K. Vetter, J.H. DeLong, A.J. Della Penna, K.M. Ha, B.N. Kosciuk, J. Mead, I. Pinayev, O. Singh, Y. Tian
  BNL, Upton, Long Island, New York

An internal R&D program has been undertaken at BNL to develop an RF BPM to meet all requirements of both the injection system and storage ring. The RF BPM architecture consists of an Analog Front-End (AFE) board and a Digital Front-End board (DFE) contained in a 1U 19" chassis. An external passive RF signal processor has been developed that will be located near the RF BPM pickups. The partitioning into two boards enables a flexible Software Defined Instrument. A model-based design flow has been adopted utilizing AWR VSS, Simulink, and Xilinx System Generator for algorithm development and AFE impairment performance analysis. The DFE architecture consists of a Virtex-6 with MicroBlaze embedded processor. An optional Intel Atom SBC is also supported. The AFE is based on a bandpass sampling architecture utilizing 16-bit ADCs. Long-term drift is corrected by inclusion of an out-of-band calibration tone. An RF BPM Calibration Tool is being developed for removal of systematic errors and performance verification. In this contribution we will present a detailed overview of the architecture, compare simulation results to laboratory performance, and report beam test results.