LBNL, Berkeley, California
A hardware system that acquires and stores a large buffer of bunch-by-bunch 16-bit data has been realized. A high resolution (up to 16-bit) analog-to-digital converter (ADC), or bank of ADCs, samples the analog signal at the bunch frequency. The digitized data is fed into a Field Programmable Gate Array (FPGA), which contains an interface to a bank of double data rate (DDR) SDRAM type memory. With appropriate data bus widths, the FPGA bursts the ADC data into the DDR SDRAM fast enough to keep up with the bunch-by-bunch ADC data continuously. The realized system demonstrates continuous data transfer at a rate of 1 GByte/sec, or 16-bit data at 500 MHz, into a 64MByte SDRAM. This paper discusses the implementation of this system and the future of this architecture for bunch-by-bunch diagnostics.
