MP531 (POSTER)
	An FPGA based multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC		113
	D. Domínguez, J.J. Gras, J. Lewis, J.J. Savioz, J. Serrano (CERN) F.J. Ballester (UPV)
	MP532 (POSTER)
	PLL Usage in the General Machine Timing System for the LHC		116
	P. Álvarez, D. Domínguez, J. Lewis, Q. King, J. Serrano, B. Todd (CERN)
	MP533 (POSTER)
	Nanosecond level UTC timing generation and stamping in CERN's LHC		119
	J. Serrano, P. Álvarez, D. Domínguez, J. Lewis (CERN)
	MP535 (POSTER)
	The evolution of the CERN SPS timing system for the LHC era		125
	J. Lewis, J.C. Bau, J. Serrano, D. Domínguez, P.A. Sanchez (CERN)